In the fabrication of integrated circuit (IC) devices (also referred to as semiconductor devices), many processes, steps, and techniques may be applied to form components and materials into the desired products. For example, in the fabrication of high-performance extremely thin semiconductor-on-insulator (ETSOI) structures/devices (e.g., extremely thin silicon-on-insulator structures, planar depleted device architectures, etc.), back-gate biases (e.g., substrate bias, body effects to threshold voltages, etc.) may be desired to tune device characteristics, manage power consumption, etc. Fabrication of these devices typically includes implantation of the substrate through a top ETSOI structure and/or wafer bonding following substrate implantation. However, implantation through the ETSOI structure may create dopant contamination in the ETSOI structure and may damage the crystal structure of the ETSOI structure, resulting in poor device performance and reliability. Further, wafer bonding during the fabrication of these devices may produce dopant diffusion throughout the structure due to the thermal budget of the subsequent bonding steps.